//-----------------------------------------------
//    module name: 
//    author: Liang
//  
//    version: 1st version (2021-10-01)
//    description: 
//        
//
//
//-----------------------------------------------
`timescale 1ns / 1ps
`include "/team/riscv/rtl/riscv.h"
module cpu_core_top(
    input [4:0]  i_intFlag_5,
    input           rstn,            
    input           clk   
    );
    
    wire [31:0] w_instAddr_32;
    wire [31:0] w_icacheInst_32;
    wire [3:0]  w_storeWen_4;
    wire [31:0] w_wDcacheData_32;
    wire [31:0] w_rDcacheData_32;
    wire [31:0] w_storeAddr_32;
    wire clk_memory;
`ifdef DC_ClKTREE 
    
    `CLKBUFF buf_clk_16 (.A(clk),.Z(clk_memory));

`else
    assign  clk_memory = clk;

`endif
    
        
    cpu_core cpu_core(
        .clk                (clk),
        .rstn               (rstn),   
        .i_intFlag_5        (i_intFlag_5),

        .o_instAddr_32      (w_instAddr_32),
        .i_instData_32      (w_icacheInst_32),

        .o_dataWen_4        (w_storeWen_4),
        .o_dataAddr_32      (w_storeAddr_32),
        .o_writeData_32     (w_wDcacheData_32),
        .i_readData_32      (w_rDcacheData_32),
        
        .dbus_rsp_valid_i    (1'b1)
    );
    
    socmem socmem(
        .rstn(rstn),
        .clk (clk_memory),

        .i_iwen_4(4'b0),          
        .i_iaddress_32(w_instAddr_32), 
        .i_idataW_32(32'b0),  
        .o_idataR_32(w_icacheInst_32),

        .i_dwen_4(w_storeWen_4),          
        .i_daddress_32(w_storeAddr_32), 
        .i_ddataW_32(w_wDcacheData_32),  
        .o_ddataR_32(w_rDcacheData_32),
        
        .req_valid_i(1'b1)
    );
    
endmodule
